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System-level modeling is to achieve
better cost-performance trade-off, short time to market, understanding of
success and failure of the system and optimizing the design space early in the
design stage. The models at the higher level of abstraction are generic, in the
sense that they can handle a variety of components, Performance numbers are
generated by simulating these models. Simulation-based system-level modeling
and analysis involve dynamic and statistical computation of design matrices at different
workload events and transitions. This method is faster than RTL (Register
Transfer Level) and more accurate than Analytical method. Hence this method is
the better choice to achieve the faster simulation and accurate results
compared to other methods. Construction of system level simulation model of the
embedded system involves data collection, defining modeling objectives,
selection of existing modeling components and templates for building custom
modeling component. One of the challenges of this approach requires more
learning in understanding the modeling concepts and to select right system
modeling components or templates at different levels of abstraction for
different modeling languages. The proposed approach involves the optimizing
long learning curve and modeling effort by exploring the systematic system
modeling approach, demonstrating automatic extraction of system modeling
components and instruction for modeling steps from the questionnaires based on
system goals and description. And batch simulation is done for faster
simulation. In this work, we discussed modeling flow starts from the idea or
system specification with modeling objectives to the optimized, validated and
executable specification for further implementation. System architecture and
task mapping are determined based on the analysis and optimization of the end
to end latency, resource cost, and utilization. Proposed work carried out using
VisualSim a Simulation-based system-level modeling tool. VisualSim includes
built-in library blocks for performance and power modeling of embedded system
components and with built-in discrete event simulator. The simulation technique
aims at reproducing only the event timings, ignoring actual data transfers and
computations. System components such as multi-core processor, memory, and bus
and IO unit can be characterized by generalized standard abstract modeling

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